Circuits over monoids: a fault model, and a trade-off between testability and circuit delay

H.A Farhat; J.C Birget

doi:10.1016/0893-9659(92)90064-G

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Circuits over monoids: a fault model, and a trade-off between testability and circuit delay

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Circuits over monoids: a fault model, and a trade-off between testability and circuit delay

H.A Farhat and J.C Birget

Applied mathematics letters, Vol.5(5), pp.55-58

1992

DOI: https://doi.org/10.1016/0893-9659(92)90064-G

Abstract

We introduce a new fault model for evaluation circuits and prefix circuits over a transformation monoid. For evaluation circuits we give a trade-off between the delay of the circuit and the number of test-inputs needed to detect faultiness.

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Title: Circuits over monoids: a fault model, and a trade-off between testability and circuit delay
Creators: H.A Farhat - Department of Mathematics and Computer Science University of Nebraska, Omaha, Nebraska 68182, U.S.A
J.C Birget - Department of Computer Science and Engineering University of Nebraska, Lincoln, NE 68588, U.S.A
Publication Details: Applied mathematics letters, Vol.5(5), pp.55-58
Date published: 1992
Publisher: Elsevier Ltd
Academic Unit: Computer Science (FASC)
Language: English
Resource Type: Journal article
Identifiers: 991031665051004646