Abstract
Greater gains in manufacturing efficiency are realized as the focus in quality engineering turns from product inspection and process control to off-line quality control, that is, improvement in the design of the product or the manufacturing process. In electronics assembly the goal of an off-line quality control project is to increase yield, the fraction of circuit boards that have no defects. The Pareto Chart, which ranks defect types according to the frequency with which they occur, is often used to select the most important off-line project. In surface mount technology, for example, such charts are generated by the expert inspection systems that evaluate the circuit boards. We show that the Pareto chart may not lead to die most important off-line project due to die clustering and high variability of some defect types in electronics assembly. New measurements, yield loss and conditional yield loss, are proposed for ranking defect types to identify the off-line projects that will lead to substantial increases in yield.